This invention relates to a semiconductor integrated circuit (IC) comprising polycell functional blocks for which a mask pattern is patterned in accordance with a layout design by an automatic placement and routing digital computer. This invention relates furthermore to an operating system for such a digital computer.
In the integrated circuit, the functional blocks are integrated typically employing gate array large-scale integration (LSI) and/or standard cell large-scale integration. It will later be exemplified that each functional block comprises a plurality of macroblocks and that each macroblock comprises a plurality of rectangular basic cells having a substantially common height.
In the manner which will later be described more in detail, the mask pattern has conventionally been given a pattern based only on connection data of connection of the macroblocks in each of the functional blocks. By reading the connection data, a conventional automatic placement and routing digital computer has produced pattern data of the mask pattern by three successive stages of placement, global routing, and detailed routing. During the placement, constructive initial placement is combined with iterative improvement. Such placement, global routing, and detailed routing are described in various references as, for example, in a handbook called "LSI Handobukku" (LSI Handbook) edited by the Institute of Electronics and Electric Communication Engineers of Japan and published in 1959 by Oomu-sya (transliterated in accordance with ISO 3602), under Item 3.2 "Reiauto Sekkei" (Layout Design).
Inasmuch as only the connection data are used, the present inventors have found it difficult to achieve optimized placement of the basic cells in each of the macroblocks by the constructive initial placement and the iterative improvement. In other words, it has been difficult to produce an optimum mask pattern by attaining shortest possible connections for the basic cells of the functional blocks and best possible electric characteristics of the functional blocks, such as a highest possible operation speed and a small power consumption. In particular, these drawbacks are unavoidable when the integrated circuit comprises a bit-sliced structure, such as an arithmetic and logical unit (ALU) and/or a multiplier.